Cisco Silicon One Q211 and Q211L Processors Data Sheet

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Updated:March 11, 2021

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Table of Contents



Value statement

The silicon industry has always been plagued with the trichotomy of switching silicon, routing line card silicon, and routing fabric silicon. Using these three basic building blocks, silicon and system vendors created unique architectures tuned for individual markets and industries. Consequentially, forcing customers to consume and manage these disjointed and dissimilar products caused an explosion in complexity, CapEx, and OpEx for the industry.

The Cisco Silicon One architecture ushers in a new era of networking, enabling one silicon architecture to address a broad market space, while simultaneously providing best-of-breed devices.

At 8 Tbps, the Cisco Silicon One Q211L builds on the ground-breaking technology of the Cisco Silicon One Q200L, Q201L, and Q202L, but also brings the efficiency and flexibility of Cisco Silicon One and 7 nm enabled 80x100GE, 40x200GE, and 20x400GE leaf and Top-of-Rack (TOR) switches. The Q211 provides similar advantages for the WAN and peering routers, enabling an 8-Tbps deep-buffered and high-scale router.

Product overview

The Cisco Silicon One Q211 processor is an 8-Tbps, full-duplex, standalone routing processor with deep buffers, while the Q211L is an 8-Tbps, full-duplex, standalone switching processor.

The Cisco Silicon One Q211 can be used to build fixed form factor routers ideally targeted for core, peering, and DCI applications, while the Cisco Silicon One Q211L can be used to build fixed form factor switches ideally targeted for data center leaf and top-of-rack applications.

Form Factors

Figure 1.            

Form Factors

Features and benefits

Table 1.        Architectural characteristics and benefits



Unified architecture across multiple markets

Greatly simplifies customer network infrastructure deployments

Unified SDK across market segments and applications

Provides a consistent point of integration for all applications across the entire network infrastructure

High-performance routing and switching silicon

Achieve line rate at small packet sizes

Power-efficient routing and switching silicon

The power efficiency of 7 nm and the Cisco Silicon One architecture

Large and fully unified packet buffer

Fully shared on-die buffer with optional large, external packet buffer

Switching efficiency with routing features and scale

Addresses the requirements of service provider and web-scale providers’ routing and switching applications

Run-to-completion network processor

Provides feature flexibility without compromising performance or power efficiency

P4 programmable

A programmable device to allow for rapid feature development

Prominent feature

Flexibility, performance, and scale for next-generation web-scale networks

Block Diagram

Figure 2.            

Block Diagram


      160 56G SerDes; each can be configured independently to operate in 10G/25G/50G using NRZ or PAM4 modulation

      Flexible port configuration supporting 10/25/40/50/100/200/400 Gbps

      Large, fully shared, on-die packet buffer

      Large, in-package packet buffer (Q211 only)

      1588v2 and SyncE support with nanosecond-level accuracy

      On-chip, high-performance, P4-programmable host NPU for high-bandwidth offline packet processing (for example, OAM processing and MAC learning)

      Multiple embedded processors for CPU offloading

Traffic management

      Large pool of configurable queues, supporting DiffServ and hierarchical QoS

      Support for system-level, end-to-end QoS and scheduling for both unicast and multicast traffic

      Support for ingress and egress traffic mirroring

      Support for link-level (IEEE802.3x), PFC priority-level (802.1Qbb) flow control and ECN marking

      Support of port extenders


      Run-to-completion, distributed, P4-programmable NPU architecture

      Line rate at very small packets with complex packet processing

      Large and shared NPU fungible tables

      Support of demanding packet processing features without impacting data rate

      Support of simple packet processing features while optimizing power and latency

Load balancing

      Flow load balancing using ECMP or LAG

      Dynamic flowlet load balancing with ability to detect and handle elephant flows

Instrumentation and telemetry

      Programmable meters used for traffic policing and coloring

      Programmable counters used for flow statistics and OAM loss measurements

      Programmable counters used for port utilization, microburst detection, delay measurements, flow tracking, elephant flow detection, and congestion tracking

      Traffic mirroring: (ER)SPAN on drop

      Support for sFlow and NetFlow

      Support for in-band telemetry


      APIs provided in C++ and Python

      SAI and SONiC support

      Configurability via high-level networking objects

      Distribution-independent Linux packaging

      Robust simulation environment enables rapid feature development

      CPU packet I/O through native Linux network interfaces

P4 programmability

      Application development is handled by a P4-based IDE programming environment

      At compilation, the P4 application generates low-level register/memory access APIs and higher-level SDK Application APIs

      Provides application support for a wide range of data center, service provider, and enterprise protocols

      Ability to develop the SDK and applications running over the SDK over a simulated Cisco Silicon One device

Cisco P4 Application

Due to Silicon One’s extensible P4 programming toolkit, we are always adding features to address new markets and new customer requirements; however, a sample of the features that are currently available with the P4 code is provided below:

Table 2.        Cisco P4 Applications




  MPLS Forwarding





    L3VPN, 6PE, 6VPE

    BGP LU



  Ethernet Switching

    802.1d, 802.1p, 802.1q, 802.1ad

  IP Tunneling

    IP in IP



  Integrated Routing and Bridging (IRB)
  Policy-Based Routing
  Security and QoS ACLs
  ECMP and LAG (802.3ad)





  Protection (Link/Node/Path and TI-LFA)
  QoS Classification and Marking
  Congestion Management

    NetFlow, sFlow

    In-Band Telemetry


    Packet Mirroring with Appended Metadata

    Lawful Intercept

  DDoS Mitigation

    Control-Plane Policing

    BGP Flowspec

  Timing and Frequency Synchronization



Product sustainability

Information about Cisco’s Environmental, Social, and Governance (ESG) initiatives and performance is provided in Cisco’s CSR and sustainability reporting.

Table 3.        Cisco environmental sustainability information

Sustainability Topic



Information on product-material-content laws and regulations


Information on electronic waste laws and regulations, including our products, batteries, and packaging

WEEE Compliance

Information on product takeback and reuse program

Cisco Takeback and Reuse Program

Sustainability inquiries



Product packaging weight and materials


For more information

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